flashinfer.msa_ops.msa_icp_decode_score_publish

flashinfer.msa_ops.msa_icp_decode_score_publish(index_q: Tensor, index_k: Tensor, block_table: Tensor, seq_lens: Tensor, num_valid_pages: Tensor, pool: Tensor, recv_bases: Tensor, errors: Tensor, *, rank: int, world_size: int, page_size: int, decode_query_len: int, slot: int, capacity: int, force_begin_blocks: int, force_end_blocks: int, spin_limit: int = 67108864, generations: Tensor | None = None, enable_pdl: bool = True, backend: str = 'cake') → None

Warning

MiniMax-M3 ICP indexer kernels (sharded index scores, Top16 select/publish, merge) is experimental: it provides no compatibility guarantees and may change or be removed without deprecation.

Fused decode scorer and publisher: the receive rows equal those of

msa_icp_decode_index_score_sharded() followed by msa_icp_topk_select_publish(), without the score rows.

pool is uint8 scratch of msa_icp_decode_pool_bytes() bytes. The other parameters are as in those two functions. With enable_pdl on compute capability 10.7 with 32 or 64 local K rows per page (P128 TP4 and TP2, P256 TP4), this scorer reads seq_lens and block_table and starts loading the history index_k pages before it waits on the preceding kernel, with the same requirement on that kernel as msa_icp_decode_index_score_sharded().

This path is an option; the default decode chain (and the facade’s decode without pool) is the score plane and the select publish, except that the facade runs this path in its own pool on compute capability 10.7 at P128 (TP2 and TP4) from 8 requests on. Each request is cut into min(clamp(num_sms * ctas_per_sm // batch, 1, 128), cap) splits, cap the architecture’s TOPK16_SPLIT_CAP (48), from host metadata only.