flashinfer.comm.get_pcie_ipc_reduce_scatter_launch_config

flashinfer.comm.get_pcie_ipc_reduce_scatter_launch_config(world_size: int, shard_numel: int, max_blocks: int = 64, element_size: int = 2, ordered_4plus4: bool = False) → PcieIpcReduceScatterLaunchConfig | None

Return a deterministic reduce-scatter launch seed.

Parameters:

  • world_size (int) – Number of ranks in the collective: 2, 4, or 8.

  • shard_numel (int) – Number of output elements on each rank, not the full reduction input. The output must occupy a positive, whole number of 16-byte packs.

  • max_blocks (int, optional) – Workspace block capacity and launch-grid limit, from 1 to 64.

  • element_size (int, optional) – Bytes per element: 2 for BF16/FP16 or 4 for FP32. Defaults to 2.

  • ordered_4plus4 (bool, optional) – Whether topology discovery verified the supported TP8 placement with logical ranks 0-3 and 4-7 forming the two four-GPU islands. Required for TP8; not required for TP2 or TP4.

Returns:

Conservative launch configuration, or None for unsupported inputs or TP8 placement. This is a seed policy, not a tuning result.

Return type:

Optional[PcieIpcReduceScatterLaunchConfig]