flashinfer.comm.UlyssesPciePlan

class flashinfer.comm.UlyssesPciePlan(numa_nodes: Tuple[int, ...], nic_names: Tuple[str, ...], transport: str = 'hybrid', gid_indices: Tuple[int, ...] = (), requested_route: str = 'auto')

Group-wide route plan for the explicit PCIe backend.

transport is "p2p" for an all-CUDA-copy route, "hybrid" for same-NUMA CUDA copies plus cross-NUMA mlx5, or "rdma" for per-rank mlx5 to every peer. Fields are indexed by process-group rank; they describe the sysfs plan and are runtime-verified by native initialization. A P2P plan has an empty GID tuple because it never opens an RDMA QP. requested_route records the joint FLASHINFER_ULYSSES_PCIE_ROUTE setting the plan was derived from.

__init__(numa_nodes: Tuple[int, ...], nic_names: Tuple[str, ...], transport: str = 'hybrid', gid_indices: Tuple[int, ...] = (), requested_route: str = 'auto') → None

Methods

__init__(numa_nodes, nic_names[, transport, ...])

Attributes

gid_indices
requested_route
transport
numa_nodes
nic_names